Generally, a conventional TTL type (.times.8, .times.16) magnitude comparator which is intended to determine the validity and magnitudes of a plurality of serially input data, is capable of comparing only fixed data having a preset bit number.
FIG. 1 illustrates a conventional logic circuit for comparing and outputting only the fixed data after receipt of serially input data.
First, 9-bit input data is added in an adder 10 consisting of a half adder HA and two full adders FA, and in other adders 20,30 respectively consisting of three full adders FA. Then NAND gates 1,2,3 receive the adder data S0-S8 and output them in the form of combined data consisting of 3 bits respectively. The output data of the NAND gates 1,2,3 are input into a NOR gate 7 which outputs only the data having a certain level (A=B) among the 9-bit input data. Meanwhile, the full adder FA which is connected to a carrier transmitting terminal CY of the adder 30 receives only predetermined data in accordance with the transmitted carriers of the adder 30, and the added output of the full adder FA is input into a NAND gate 4 and NOR gate 8. Then the output data of the full adder FA and the output data of the NOR gate 7 are input into the NAND gate 4 after being inverted by an inverter IN2 which discriminates the magnitudes (A&gt;B) of uppermost bits MSB.
Further, the output data of the full adder FA together with the output data of the NOR gate 7 are also input into NOR gate 8 in which the magnitudes (A&lt;B) of lowermost bits LSB are discriminated.
Further, the equivalent data and the data of the lowermost bits are also applied to still another NOR gate 9 from which address bits of a certain level are output after being inverted by an inverter IN3.
In the conventional magnitude comparator constituted as described above, if it is made of a serial semiconductor device receiving the data of variable bit numbers, a plurality of the input data have to be discriminated by comparing them bit by bit, thereby making it difficult to operate them.
Further, the above described conventional magnitude comparator is constituted such that the input and output data are handled in a parallel form. Therefore, in a serial input/output semiconductor device, if the bit numbers of the input data or the bit numbers of the internal data is varied, the circuit constitution of the comparator becomes very complicated, while increasing the number of the input gates, and therefore, the integration of the semiconductor device has to be lowered.